The present invention relates to an apparatus and method of forming self-aligned conductive plugs between a conductive line and a conductive region.
In the semiconductor manufacturing industry, the concept of dual damascene is utilized to form conductive plugs and conductive lines in a self-aligned manner to electrically connect two conductive regions. Although the concept of forming conductive lines and conductive plugs has many advantages, there are several shortcomings. One shortcoming is the potential of misalignment of conductive plugs and conductive lines due to small misalignments that are typical in submicron technologies. The following is a description of a dual damascene conductive line and conductive plug formation and how this formation may be compromised by small misalignments.
FIG. 1A depicts five layers of material that are deposited over one another. The bottom layer is a semiconductor substrate 10. The semiconductor substrate 10 may comprise different regions with different characteristics and materials typical of semiconductor devices. Over the semiconductor substrate 10 is a conductive region 12. FIG. 1A shows conductive region 12 running along the page, however, the conductive region 12 can be surrounded by material that electrically isolates the conductive region 12. Over conductive region 12 dielectric layer 14 is formed. It is through dielectric layer 14 that a conductive plug will eventually be formed. Over dielectric layer 14 an etch stop layer 16 is formed. The etch stop layer 16 is intended to be patterned in a subsequent step and is intended to define the dimensions of the conductive plug to be formed through dielectric layer 14. Finally, in FIG. 1A, a resist layer 18 is deposited over the etch stop layer 16.
FIG. 1B depicts the layers of FIG. 1A, after the resist layer 18 has been etched using photolithography to form an opening 20 down to the etch stop layer 16. The opening 20 in the resist layer 18 defines how the etch stop layer 16 will be patterned and ultimately defines the shape of the conductive plug in the dielectric layer 14.
FIG. 1C depicts the layers of FIG. 1B, after the etch stop layer 16 has been patterned or etched as defined by the opening 20, of FIG. 1B, in resist layer 18. Accordingly, opening 20 extends through the etch stop layer 16 to form opening 21, which in a subsequent step will define the shape of a conductive plug formed in dielectric layer 14.
FIG. 1D depicts the layers of FIG. 1C, after the resist layer 18 has been removed. Resist layer 18 is no longer necessary, as its purpose was to define opening 22 in etch stop layer 16. FIG. 1E depicts the layers of FIG. 1D, after a second dielectric layer 24 is formed over the first dielectric layer 14 and the etch stop layer 16. Further, a resist layer 26 is formed over the second dielectric layer 24.
FIG. 1F depicts the layers of FIG. 1E after an opening 28 is formed in the resist layer 26. Opening 28 may be created through conventional photolithography techniques. The opening 28 is shaped to define a trench that will be formed in second dielectric layer 24 in a subsequent step.
FIG. 1G depicts the layers of FIG. 1F after an opening 30 has been formed through the first dielectric layer 14 and the second dielectric layer 24. This opening 30 can be formed by a single anisotropic etch step or multiple anisotropic etch steps that etch through the second dielectric layer 24 to form a trench and through the first dielectric layer 14 to form a via. The first dielectric layer 14 and the second dielectric layer 24 can be etched either in one step or selectively etched in two steps. The portion of the opening 30 that is proximate to the first dielectric layer 14 is defined by the opening 22 in etch stop layer 16. As shown in FIG. 1H, after the first dielectric layer 14 and the second dielectric layer 24 are etched, the resist layer 26 is removed. One method for the removal of the resist layer 26 is a polishing process. After the removal of the resist layer 26, the opening 30, of FIG. 1G, is reduced to opening 32. As shown, in FIG. 1I, opening 32, of FIG. 1H, is filled with a conductive material 34. The conductive material 34 forms both a conductive line and a conductive plug. The conductive plug electrically connects the conductive line to the conductive region 12.
FIG. 2A is a top view of an ideal dual damascene formation which connects a lower conductive region 40 with conductive line 38 through a conductive plug, wherein the conductive plug is defined by opening 42 in an etch stop layer. For simplification, it is shown that conductive line 38 runs in a vertical direction of the page, while the lower conductive region 40 runs perpendicularly in the horizontal direction of the page. At the intersection of the lower conductive region 40 and the conductive line 38, the conductive plug is formed.
FIG. 2B is a cross-sectional view of FIG. 2A along line 2B drawn on FIG. 2A. It is shown in FIG. 2B that conductive line 38 is separated from conductive region 40 by dielectric layer 50 and etch stop layer 48. The conductive region 40 and the conductive line 38 are connected by conductive plug 43. As the formation depicted in FIG. 2B is a dual damascene formation, conductive line 38 and conductive plug 43 are integrated together and therefore must be made of the same conductive material. Conductive region 40 is in contact with conductive plug 43 and is electrically connected thereby to conductive line 38. FIG. 2C is a cross-sectional view of FIG. 2A along line 2C drawn on FIG. 2A. FIG. 2C illustrates how conductive region 40 can be formed in semiconductor substrate 10.
One aspect of FIGS. 2A-2C, that one of ordinary skill in the art would appreciate, is that the conductive plug 43 is perfectly aligned between the conductive line 38 and the conductive region 40 and the via which the conductive plug 43 fills is entirely defined by the opening 42 in the etch stop layer 48.
FIGS. 3A-3C illustrate a typical dual damascene formation of the prior art, that is similar to the dual damascene formation illustrated in FIGS. 2A-2C. However, a disadvantage is illustrated of misalignment and deformation of conductive plug 61. FIG. 3A is a top view of such a dual damascene formation. FIG. 3B is a cross-sectional view of FIG. 3A along line 3B. FIG. 3C is a cross-sectional view of FIG. 3A along line 3C.
In FIGS. 3A-3C it is illustrated that conductive plug 61 is not aligned correctly under conductive line 54. As shown in FIG. 3B, it was intended for the conductive plug 61 to be defined by an opening 58 in the etch stop layer 66. However, because of misalignment of opening 58, only a portion of the intended conductive plug 61 is actually formed between conductive region 40 and the conductive line 54. The opening 58 is partially covered by the second dielectric layer 64, which prevents the etch stop layer 66 from adequately defining conductive plug 61, as intended, because of the misalignment. Hence, the misalignment causes conductive plug 61 to be much smaller than intended; this effect is a serious disadvantage. For instance, the dual damascene structure may be a component of a microprocessor, with the designer of the microprocessor intending for a certain current to flow through the conductive plug 61 to optimize the maximum operating speed of the microprocessor. The microprocessor will be limited by defective conductive plug 61 and will only operate at a slower, less desirable, speed than intended. Further, if the misalignment is so extreme, a conductive plug may not even be formed and the microprocessor functionality will be seriously compromised.
There are a number of disadvantages to conventional dual damascene methods of formation. One of these disadvantages is that there is a very limited tolerance to misalignments of an opening in the etch stop layer that is intended to define a conductive plug. As a result of such misalignment, a conductive plug can be formed smaller than intended and substantially limit the functionality of a device comprising such a compromised dual damascene formation. Another disadvantage is the possibility that an opening in the etch stop layer is completely misaligned with the conductive line, resulting in a conductive plug not being formed.
There is a need for a dual damascene method and apparatus that would mitigate the problem of misalignment of a conductive plug with a conductive line. More particularly, there is a need to prevent the performance of devices from being compromised that employ such a dual damascene formation to electrically connect a conductive region with a conductive line. Further, there is a need for a dual damascene formation that prevents the non-functionality of a device employing such a dual damascene structure because of misalignment of an opening in an etch stop layer with a conductive line.
These and other needs are met by embodiments of the present invention, which provide a method and apparatus of aligning a conductive plug with a conductive line. The present invention utilizes an enlarged opening in an etch stop layer, such that part of the conductive plug is defined by the opening in an upper dielectric layer and part of the conductive plug is defined by an opening in the etch stop layer. More particularly, the opening in the etch stop layer overlaps the opening in the upper dielectric layer, such that misalignments can be tolerated without compromising the integrity of the formed conductive plugs. The present invention further accommodates different configurations by which the conductive plugs are defined by both an opening in the upper dielectric layer and an opening in the etch stop layer.
One embodiment of the present invention accommodates these different configurations by ensuring that the size of the different conductive plug configurations are the same to maximize the performance of the device comprising such a dual damascene formation. More particularly, it is important in some types of devices that the conductive plugs be of uniform size to substantially conduct electricity at the same rate between a conductive region and a conductive line in differently configured conductive plugs.